1. Field of the Invention
The present invention relates to a circuit for protecting an internal circuit of a semiconductor device from electrostatic discharge (ESD) phenomena.
2. Description of the Related Art
Semiconductor memory devices are generally provided with input protection circuitry for protecting internal circuits of a chip from a high electrostatic voltage applied from the exterior of the chip.
While MOS circuits are optimized internally for voltages around 5 v, these circuits can encounter much higher voltages on the inputs. A MOS device is particularly sensitive to high voltage discharges which can rupture a thin gate oxide layer therein.
High electrostatic discharges can originate from the human body, which can generate charges exceeding 2000 v, or from poorly grounded equipment such as test machines.
High electrostatic discharges can also originate from noisy environments such as are encountered in automotive applications or consumer applications such as personal computers. For this reason, input protection circuitry designed to withstand voltages on the order of 2000 v or more is common in CMOS circuits.
Conventional input protection circuits, such as that shown in FIG. 1, include an ESD prevention element, such a thick field device (TFD), which is provided close to an input pad 1 of a chip input terminal.
The TFD is designed such that a field oxide layer is interposed between two n+ diffusion regions. The TFD transfers a charge from one n+ diffusion region to the other so as to undergo a punch-through effect across its channel region. As a result, an excessively high voltage current, caused by a high electrostatic discharge voltage present at input pad 1, is driven to a ground voltage terminal Vss (hereon ground).
Input pins are generally provided as input terminals to a chip. Each input pin usually includes a pad so as to buffer an externally provided input voltage thereto. Consequently, an electrostatic voltage may be adversely introduced as a signal to an input pin through contact with its input pad.
The ESD phenomena and preventive measures thereof are described in detail in an article entitled, "Internal Chip ESD Phenomena Protection Circuit", published in IEEE TRANSACTION ON ELECTRON DEVICES, PP.2133-2139, Vol.35, No.12, December 1989.
In addition, Korean Patent Application No. 91-1128 discloses a circuit, shown here as prior art FIG. 1, for preventing ESD between an input pad, a source voltage terminal, and a ground voltage terminal. An n+ diffusion region, separated by a field oxide layer, is connected between the input pad and ground such that a high voltage current introduced at the input pad and caused by static electricity is bypassed (driven) to ground.
This is accomplished by taking advantage of a technique fundamentally understood as the punch-through phenomena of an n+ diffusion region which is separated by a field oxide layer.
As explained above, FIG. 1 relates to a conventional circuit for protecting an internal circuit from electrostatic discharge. This circuit is shown connected to input pad 1 and internal circuit 20, all of which are connected by metal line 10. Internal circuit 20 receives a supply voltage Vcc and may include, for example, P-type transistor P1 and N-type transistor N1.
As explained above, the thick field device (TFD) is used to essentially bypass ESD to ground. MOS diode T1, used as a clamping circuit, is connected in parallel with the TFD element, both of which are connected between metal line 10 and ground voltage terminal Vss.
There is also provided a resistor R1 comprised of an n+ diffusion region which is connected between node 11 of metal line 10 and node 12 of metal line 10.
Resistor R1 has a high resistance value and is used to protect gate oxide layer 21, in NMOS transistor N1 of internal circuit 20, from an ESD stress voltage.
This is because when an ESD stress voltage is applied from input pad 1 to metal line 10 (about 3000 V may be used here as an appropriate test voltage), a high voltage current is instantly discharged through the TFD. This high stress voltage potential is simultaneously dropped across resistor R1 before an excessive current can otherwise destructively drive the MOS internal circuit 20.
Consequently, ESD stress voltage is prevented from destructively affecting internal circuit 20.
However, the above conventional circuit is found to exhibit a long RC delay time .tau.1 during normal input signal transmission. This long RC delay time .tau.1 is caused by parasitic components induced between node 12 and internal circuit 20, i.e., parasitic resistance r1 and capacitances c1 and c2.
The RC delay time .tau.1 may be expressed by Eq. 1. EQU .tau.1=R1.c1+(R1+r1).c2 =R1 (c1+c2)+r1.c2 . . . (Eg.1)
If we approximate R1, r1, c1 and c2 to be, respectively, 500.OMEGA., 200.OMEGA., 2pF and 2pF, then the RC delay time .tau.1 is about 2.4 ns.
From equation 1, it should be clear that the RC delay time .tau.1 increases for greater resistances and capacitances, such values being directly affected by the length of metal line 10.
As a consequence, greater RC delay times delay the transmission speed of an input signal from input pad 1 to internal circuit 20. While resistor R1 is necessary to reduce the ESD stress voltage to internal circuit 20, its high parametric value results in the disadvantageous characteristic of excessive delay of an input signal, thus reducing overall transmission speed.